In the past, as an element isolation method for a semiconductor device having a buried layer, a technique employing deep trench isolation (hereinafter “DTI”) is known. The DTI is formed as explained below. First, a buried layer in which N-type impurities are dispersed at high concentration by using the ion implantation method is formed in a predetermined position of a P-type semiconductor substrate. An impurity region having concentration of N-type impurities lower than that of the buried layer is formed from the peripheral section of the buried layer to the semiconductor substrate. Subsequently, an N-type semiconductor layer is epitaxially grown on the semiconductor substrate on which the surface of the buried layer is exposed. Thereafter, a mask having openings for forming deep trench for element isolation is formed on the upper surface of the N-type semiconductor layer. The deep trench is formed by etching so that a bottom of the deep trench is reaching the semiconductor substrate and deeper than the impurity region. The deep trench is formed in positions in contact with the buried layer. Subsequently, after an insulation film that covers at least the inner surfaces of the deep trench is formed by thermal oxidation at 850° C. to 1,200° C., silicon oxide film is formed to fill the inside of the deep trench by the chemical vapor deposition (CVD) method and an unnecessary film on the upper surface of the semiconductor layer is removed to planarize the semiconductor layer by the chemical mechanical polishing (CMP) method. In this way, the DTI is formed (see, for example, Japanese Patent Application Laid-Open No. 2003-297845).
However, in the technique in the past, because the deep trench is formed in the position in contact with the buried layer, the buried layer is exposed in the deep trench after the deep trench is formed. Therefore, when sidewalls of the deep trench are oxidized, the N-type impurities of the buried layer diffuse outward to the sidewalls of the deep trench and N− layer is formed on the sidewalls of the deep trench. The N− layer formed below the buried layer has an action of relaxing the gradient of impurity concentration of the buried layer. Further, a depletion layer is extended. Therefore, there is an effect in improvement of element isolation breakdown voltage. On the other hand, the N− layers formed above the buried layer suppress the extension of the depletion layer and lower breakdown voltage in an element.
As a semiconductor device that requires the deep trench, besides a high-breakdown voltage semiconductor device such as a lateral double diffusion metal-oxide-semiconductor (LDMOS), there is a semiconductor device for high frequency that does not require high inter-element breakdown voltage unlike the LDMOS. However, in the past, after the deep trench is formed by the method explained above without distinguishing characteristics of these semiconductor devices, a semiconductor element such as a high-breakdown voltage semiconductor element or a high-frequency semiconductor element is formed in a region defined by the deep trench.